FIG. 1 is a block diagram of a portion of a conventional integrated circuit 100, which includes pad 101, delay locked loop (DLL) 102, global clock buffer 103, and global clock routing network 104. Other well-known elements of integrated circuit 100 are not illustrated in FIG. 1 for purposes of clarity. Reference clock signal REF.sub.-- CLK is applied to pad 101. The reference clock signal REF.sub.-- CLK is routed to DLL 102 as an input clock signal CLK.sub.-- IN. The CLK.sub.-- IN signal is used to clock data into integrated circuit 100. In response to the CLK.sub.-- IN signal, DLL 102 generates an output clock signal CLK.sub.-- OUT, which is provided to global clock driver 103. The output clock signal CLK.sub.-- OUT is transmitted through global clock driver 103 to global clock routing network 104. Global clock routing network 104 transmits the output clock signal CLK.sub.-- OUT throughout integrated circuit 100 with minimum skew and a significant delay. A feedback clock signal CLK.sub.-- FB is provided at the end of the global clock routing network 104. The CLK.sub.-- FB signal has a delay that is similar to the delay of the output clock signal CLK.sub.-- OUT as it is routed to other loads of the integrated circuit. The feedback clock signal CLK.sub.-- FB is used to clock data values throughout integrated circuit 100 (e.g., to clock data values out of the integrated circuit).
The feedback clock signal CLK.sub.-- FB is also provided to DLL 102. In response to the feedback clock signal CLK-FB, DLL 102 introduces a delay in the output clock signal CLK.sub.-- OUT. DLL 102 controls the amount of delay introduced, such that the feedback clock signal CLK.sub.-- FB is synchronized with the input clock signal CLK.sub.-- IN. By synchronizing the feedback clock signal CLK.sub.-- FB with the input clock signal CLK.sub.-- IN, the data clocked into integrated circuit 100 (by input clock signal CLK.sub.-- IN) is synchronized with the data clocked out of integrated circuit 100 (by feedback clock signal CLK.sub.-- FB). As a result, clock skew is eliminated, thereby eliminating signal hold time requirements, without delaying the input signals.
Integrated circuit 100 requires that pad 101 be dedicated to receiving the input clock signal CLK.sub.-- IN. Integrated circuit 100 also requires that DLL 102 receives the input clock signal CLK.sub.-- IN from pad 101. In addition, DLL 102 must receive the feedback clock signal CLK.sub.-- FB from global clock routing network 104. As a result, the flexibility of integrated circuit 100 is undesirably limited.
It would therefore be desirable to have an integrated circuit with an improved DLL interconnect structure. It would further be desirable if such an improved DLL interconnect structure could be implemented on a field programmable gate array (FPGA).